When selecting between RMII and SPI interfaces for the OCPP charging pile control board, the layout flexibility is halved

When selecting between RMII and SPI interfaces for OCPP charging pile control boards, the decision hinges on a triple trade-off among communication speed requirements, MCU resource utilization, and PCB space constraints. In 2026's mainstream solutions, RMII dominates the high-end market at 70%, while SPI leads in cost-sensitive markets at 80%, with significant differences in PCB layout flexibility.

1. RMII: Reduced Media Independent Interface

• Technical Features: 7 pins (TXD0/1, RXD0/1, CRS_DV, REF_CLK, MDIO/MDC optional), significantly reduced from the 16 pins of MII. Clock frequency: 50MHz, REF_CLK can be externally provided or internally generated. Data width: 2 bits. At 100Mbps rate, actual throughput meets OCPP JSON+TLS encryption requirements. PHY chip is independent (e.g., LAN8720, DP83848), connected to MAC via RMII. PHY layout is close to RJ45, while MAC resides on the MCU side, enabling flexible separation.

• Advantages of the board: Fewer pins → MCU GPIO released, suitable for multi-peripheral scenarios (PLC+CAN+RS-485). PHY and MAC separated → EMI optimization, PHY mounted with RJ45, transformer isolation, MAC positioned at the center of the control board. Few high-speed signals → 50MHz single-ended lines, PCB trace length matching <2cm is sufficient, with minimal layout constraints.

• Cost: Requires external PHY chip, costing 8-15 RMB, accounting for 3-5% of BOM. REF_CLK clock tree is complex, necessitating crystal oscillator or PLL, with synchronization challenges when multiple PHYs are involved.

2. SPI: Serial Peripheral Interface

• Technical features: 4-pin interface (MOSI, MISO, SCK, CS), general-purpose interface, native MCU support. Clock <50MHz, actual speed limited by SPI controller and slave device. For Ethernet controllers like W5500 in SPI mode, theoretical speed is 25Mbps, but in OCPP scenarios, actual speed is <10Mbps. High integration, such as WIZnet W5500 with built-in TCP/IP protocol stack, allowing MCU to offload protocol processing via SPI communication.

• Board Advantages: 4 wires → minimalist wiring, only a 2-layer PCB is needed, suitable for cost-sensitive scenarios. Built-in protocol stack → no need for MCU to run lwIP, freeing up Flash/RAM, ideal for 128KB small-capacity MCUs. Single-chip solution → W5500 = PHY + MAC + protocol stack, BOM cost of 12-18 yuan, slightly cheaper than RMII + PHY + transformer.

• Cost, rate bottleneck, actual throughput of 10Mbps, OCPP heartbeat + MeterValues sufficient but firmware upgrade (FOTA 2MB package) takes several minutes, poor experience. SPI shared bus, multiple slave devices (Flash, metering chip, display) with numerous CS lines, complex logic, reduced real-time performance. Integrated protocol stack is closed, W5500's built-in TCP/IP is non-customizable, limiting features like TLS 1.3 and OCSP.

3、 Comparison of measured flexibility of fabric board

• RMII scheme, PHY with RJ45, transformer isolation, MAC in MCU, 7 wires, length matching 2cm, layout freedom. 100Mbps full speed, FOTA 2MB packet<20 seconds. BOM: PAY 10 yuan+Transformer 5 yuan+RJ45 3 yuan=18 yuan.

• SPI solution, W5500 single-chip, 4 SPI traces, any length (<20cm), 2-layer PCB through-hole layout. 10Mbps speed limit, FOTA 2MB packet>3 minutes. BOM: W5500 15 yuan+RJ45 3 yuan=18 yuan, or domestic CH395 8 yuan=11 yuan.

• Flexibility difference, RMII has multiple pins but separated layout, suitable for 4-layer HDI, multiple peripherals, and high-speed requirements; SPI pins are few but integrated with binding, suitable for 2-layer boards, cost-effective, and low-speed sufficient. In 2026, choose RMII for high-end piles (22kW/PLC/PnC) and SPI for economic piles (7kW/scan code/no FOTA).

4、 One sentence summary

RMII vs SPI is not about technical superiority or inferiority, but about scenario adaptation - RMII 7-wire switch to 100Mbps+layout freedom+protocol customization, suitable for high-end piles; SPI 4-pin switch to minimalist wiring+low cost+built-in protocol stack, suitable for economical use. By 2026, the flexibility of the board will be doubled: RMII can run any wiring on 4 layers of HDI, while SPI is limited to long-distance SPI bus competition on 2 layers of boards. Choose RMII or SPI, first check the pile positioning, then check the MCU resources, and finally calculate the BOM account.

The communication charging pile control board produced by Xincheng Technology is of high quality and good price. Welcome to inquire and purchase!